For the purposes of this description a multicore microprocessor or processor may be considered to include a single integrated circuit or circuit module having a plurality (at least two) data processors that may be capable of independent operation. Each data processor can be referred to as a “core”, and the integrated circuit or circuit module may thus be referred to as the multicore microprocessor or processor.
In a multicore microprocessor integrated circuit (chip), an across-chip delay variation can result in each of the cores exhibiting a different maximum operational frequency (which may be referred to as “Fmax”). Recently, multicore microprocessors have been developed such that each of the cores can be run asynchronously and independently, each retiring a separate stream of threads or program instructions. In those cases where the threads are dependent, e.g., where the execution of one thread is dependent on the execution of another thread, a certain transaction may not be retired until some selected thread or threads are first completed, so that their results may be provided to other threads. Such “primary” threads thus gate the overall system performance and, as a result, should be executed as fast as possible. A problem that arises is that a system instruction dispatcher operates under the assumption that all cores are equally fast (i.e., Fmax for each core are equal), where in fact this is not the case. As a result, scheduling inefficiencies arise that impact the overall performance of the multicore processor system.
Another problem relates to multicore processor power consumption control. For achieving the lowest possible power consumption in a multicore microprocessor, where one or more cores may be placed in a sleep/doze/nap (lower power) mode, it is most desirable to have the fastest of the cores awake and retiring instructions while the slowest cores are off and saving energy. The problem is that presently there is no way of knowing which cores should be awake and operational, and which should be in a low power consumption mode, when they are not all being used at the same time.
In U.S. Pat. No. 6,161,188 Gaskins et al. describe a microprocessor having selective control features to determine its core-to-bus clock ratio. The microprocessor includes a fuse and buffer/control logic. The fuse can be programmed during fabrication. When blown, the fuse provides a permanent state that prescribes a fixed core-to-bus clock ratio. The buffer/control logic is coupled to the fuse. The buffer/control logic accepts the permanent state of the fuse and directs the microprocessor to set the core-to-bus clock ratio to a fixed value, thus disabling control of the core-to-bus clock ratio via external clock ratio control signals.
In U.S. Pat. No. 6,728,892 Silvkoff et al. describe a method for conserving power in a control area network (CAN) microcontroller that includes a processor core and a CAN/CAL (CAN application layers) module that includes a plurality of sub-blocks that cooperatively function to process incoming CAL/CAN messages. The method includes the steps of placing the processor core in a power-reduction mode of operation (e.g., a sleep or idle mode of operation), placing the CAN/CAL module in a power-reduction mode of operation, and activating the CAN/CAL module to process an incoming CAL/CAN message thereby terminating the power-reduction mode of operation thereof, while the processor core is in its power-reduction mode of operation.
In US Patent Application Publication 2003/0070013 Hansson discloses a method and apparatus for reducing power consumption within a pipelined processor. In one embodiment the method comprises defining an instruction which invokes a “sleep mode” within the processor and pipeline; inserting the instruction into the pipeline; decoding and executing the instruction, stalling the pipeline in response to the sleep mode instruction; disabling memory in response to the sleep mode instruction; and awaking the core from sleep mode based on the occurrence of a predetermined event. Methods for structuring core pipeline logic and extension instructions to reduce core power consumption under various conditions are also described, as are methods and apparatus for synthesizing logic implementing the aforementioned methodology.
In US Patent Application Publication 2004/0215987, Farkas et al. describe a computer system for conserving operating power which includes a number of computer hardware processor cores that differ amongst themselves in at least in their respective operating power requirements and processing capabilities. A monitor gathers performance metric information from each of the computer hardware processor cores that are specific to a particular run of application software then executing. A workload transfer mechanism transfers the executing application software to a second computer hardware processor core in a search for reduced operating power. A transfer delay mechanism is connected to delay a subsequent transfer of the executing application software if the system operating power may be conserved by such delay.
In US Patent Application Publication 2005/0154931, Oh describes apparatus and methods for controlling power of a processor having a plurality of cores. The apparatus and methods are said to operate such that independent control is possible of individual or selected cores and power supply circuits corresponding to the cores based on, for example, an operation state of the processor or a power mode. Embodiments of an apparatus for controlling power of a processor having a plurality of cores can include a plurality of power supply units each capable of independently supplying a supply power to a plurality of cores provided in one processor, a unit for checking at least one among a use state, a use amount and a power mode of each core and for turning on/off each checked core, and a unit that contacts with the unit for checking for controlling the power supply units in response to an on/off operation of each core.
In US Patent Application Publication 2006/0212677 Fossum describes embodiments of a multicore processor having active and inactive execution cores. In one embodiment an apparatus includes a processor having a plurality of execution cores on a single integrated circuit, and a plurality of core identification registers. Each of the plurality of core identification registers corresponds to one of the execution cores to identify whether the execution core is active.
In US Patent Application Publication 2004/0158747 Kim discloses a processor that includes a processor core and at least one peripheral device. A selecting circuit is used for determining an operational state of the processor and for outputting a selection signal based on the evaluation. A high-speed control circuit controls high-speed operations of at least one of the processor core and the peripheral device in response to the selection signal, and a low-speed and low-power control circuit controls low-speed and low-power operations of at least one of the processor core and the peripheral device in response to the selection signal.
In US Patent Application Publication 2002/0018486 Musoll et al. describe a logic system in a data packet processor that is provided for selecting and releasing one of a plurality of contexts.